1. Field of the Invention
This invention relates to the fabrication of flip-chip integrated circuit devices, and more particularly, to a thermal expansion matching, low alpha particle emitter substrate having an insulated layer upon which to deposit metallized circuit patterns for making electrical contact with a flip-chip.
2. Description of the Related Art
Flip-chip technology involves plating metallized bumps on selected portions of the metallized pattern on the active face of a flip-chip, and mounting the flip-chip with its active face against a substrate. The bumps on the flip-chip may be reflow soldered to a metallized circuit pattern on the surface of the substrate. The metallized pattern on the substrate may be electrically connected to external circuitry by such means as the pin grid contactor described in the above-referred to U.S. Pat. application, Ser. No. 007,833, filed Jan. 26, 1987. Flip-chips are especially useful where a large number of electrical connections must be made with the integrated circuit, such as from two hundred to three hundred.
Because a flip-chip is mechanically locked to a substrate by the reflow solder joints between the flip-chip bumps and the substrate, the substrate material must have a coefficient of thermal expansion which closely matches that of the semiconductor material of which the integrated circuit is constructed. Otherwise, thermally generated shear forces between the flip-chip and the substrate can develop which are strong enough to damage the flip-chip or the substrate. In addition, the substrate material must have good thermal conductivity to prevent heat build-up in the integrated circuit chip, and must be inexpensive, durable, and readily processed for the addition and patterning of metallic conductors on its surface. An additional requirement is that, in the case of dynamic random access memory chips, or other semiconductor devices which are sensitive to soft errors caused by alpha particles, the substrate must not be an emitter of alpha particles. Also, the metallic conductors on the surface of the substrate must be on a dielectric surface to prevent inadvertent shorting of the integrated circuit.
In the case of flip-chips constructed of silicon, a suitable substrate material has been found in silicon carbide. Silicon carbide has a coefficient of thermal expansion closely matching that of silicon, it is inexpensive, and possesses sufficient mechanical strength to be used as a substrate. A shortcoming of silicon carbide, however, is that it is not a good enough insulator or dielectric to prevent inadvertent shorting or electrical interference of one flip-chip contact with another. It is desirable that the substrate resistivity be on the order of 100 tera-ohm-cm or more. Pure silicon carbide has a resistivity of approximately 1000 ohm-cm, which is far too low.
Prior art solutions to the resistivity problem have focused upon modifying the entire silicon carbide substrate by adding other ceramics to it, such as beryllium oxide, yttrium oxide, aluminum oxide, or silicon oxide, to achieve higher resistances. However, such modifications result in such adverse consequences as increased cost, increased toxicity due to the beryllium, and an adverse change in the dielectric constant of the modified silicon carbide. In addition, the coefficient of thermal expansion of the substrate can be adversely changed by such additions to the silicon carbide so that the coefficient for the substrate no longer closely matches that of silicon.
Modern VLSI integrated circuit chips have grown to such a size that it is not uncommon to find one requiring from two to three hundred electrical contacts to the external world. For every such contact, an external lead or pin is required to make electrical contact between the chip and external circuitry as may be found on a printed circuit board. For VLSI chips of this size, older package styles, such as DIP's, have proven to be inadequate since they would require an extremely large package size to accommodate the necessary number of pins or leads VLSI chips of this large size are often logic parts such as ECL gate arrays.
One of the answers to the problem of developing a very high pin count package is the pin grid array package style. Older package styles have pins or leads which protrude from one to four sides of a rectangular package. The pin grid array package typically is square and may have from one to several rows of pins protruding from the peripheral portions of its bottom surface. An example of such a pin grid array package 1 is shown in FIG. 1. The illustrated device has sixty pins 2 protruding from its bottom surface 3. These pins 2 are for insertion into a socket or plated through holes in a printed circuit board.
One of the present methods of electrically connecting an integrated circuit chip to the pins of a pin grid array is illustrated in FIG. 1. The integrated circuit chip 4 is mounted in the bottom surface 3 of the pin grid array package 1, and is connected to the pins 2 via bond pads 5, bond wires 6 and metallized leads 7. For simplicity, FIG. 1 shows only two such electrical connections. Experience has shown that the bond wire method of forming the electrical connections becomes very difficult with pin grid array packages having more than two hundred pins. This is due to the difficulty of forming the wire bonds in very close proximity to each other. A further disadvantage of wire bonding is that it is an expensive, labor intensive process, requiring costly machinery and materials such as gold wire, and requiring considerable human intervention. Furthermore, wire bonds are subject to breakage, for instance, during the packaging process.
There have been attempts to get larger pin counts from a pin grid array device by using flip-chips. Flip-chips have metallized bumps plated at contact points on the metallized circuit pattern which is on the face of the chip. The bumps at the contact points are for contact with external circuitry, and are used in lieu of wire bonds. The substrate for mounting the flip-chip has a metallized circuit pattern on its face and contact points for electrically contacting the bumps on the face of the flip-chip. Typically, the bumps are soldered to the contact points on the substrate. The metallized patterns on the surface of the substrate are in electrical contact with the pins of the completed integrated circuit device.
Flip-chips have been used in prior art pin grid array devices, however, they must be used in thermally stable environments since these prior art devices utilize flip-chips and substrates having dissimilar coefficients of thermal expansion. Large enough temperature variations cause such devices to develop shear forces between the flip-chip and substrate sufficiently large to cause damage to the device.
Not solved by the prior art is the problem of finding a suitable substrate possessing all the desired properties of a pin grid array device. That is, the substrate must have a high coefficient of thermal conductivity in order to dissipate the heat built up in the operating flip-chip; the substrate should have a coefficient of thermal expansion close to that of the semiconductor material of which the flip-chip is comprised in order to allow the assembled pin grid array device to be operated in a variety of ambient temperatures; the substrate must be mechanically rugged; and the substrate should allow the mounting of pins for making electrical contact between the assembled pin grid array device and external circuitry.